Resonant clock distribution networks have recently been proposed for the energy-efficient distribution of clock signals in synchronous digital systems. In these networks, energy-efficient operation is achieved using one or more inductors to resonate the parasitic capacitance of the clock distribution network. Clock distribution with extremely low jitter is achieved through reduction in the number of clock buffers. Moreover, extremely low skew is achieved among the distributed clock signals through the design of relatively symmetric all-metal distribution networks. Overall network performance depends on operating speed and total network inductance, resistance, size, and topology, with lower-resistance symmetric networks resulting in lower jitter, skew, and energy consumption when designed with adequate inductance.
In resonant clock distribution networks, the amount of energy injected into the clock network depends on certain design parameters, including the size of the final clock drivers, and the duty cycle of the reference clock signals that drive the final clock drivers. Furthermore, in contrast to conventional (that is, non-resonant) clock distribution networks, the amount of energy injected into the resonant network also depends on the frequency at which the network is operated. In general, larger driver sizes or longer duty cycles allow for more current to build up in the inductive elements, thus ultimately injecting more energy into the clock network, and resulting in faster clock rise times or larger clock amplitudes. Moreover, for fixed driver size and duty cycle, operation at a low frequency results in faster clock rise times and larger clock amplitudes than operation at a relatively higher frequency, since the final clock drivers conduct for a longer time, thus again allowing for more current to build up in the inductive elements and the injecting of more energy into the clock network.
In conventional clock distribution networks, drivers are generally sized to yield a target rise time and clock amplitude for the highest frequency at which the clock is operated at. In those designs, the amount of energy injected into the clock network is always the same, regardless of driver size, duty cycle of the reference clock, or operating frequency, assuming that at the peak frequency of the clock drivers are sufficiently large to yield the target clock rise time and clock amplitude. Therefore, rise time and clock amplitude remain largely unchanged at any other clock frequency that is lower than the peak clock frequency. Moreover, the amount of energy injected into the clock network is always the same, regardless of operating frequency.
The distribution of clock signals using resonant clock distribution networks presents particular challenges in the context of digital devices that are specified to operate at multiple clock frequencies. For example, a high-performance microprocessor may be designed to operate at multiple clock frequencies ranging from 100 MHz to 3 GHz. Resonant clock distribution networks are generally designed to achieve their highest energy efficiency when operating in resonant mode, and within a relatively narrow range of clock frequencies that are centered about the natural frequency of the resonant clock network. It is possible for resonant clock networks to operate outside this narrow range, but to maximize energy efficiency, the size of the clock drivers or the duty cycle of the reference clock input to the network needs to be adjusted depending on clock frequency.
Unlike non-resonant clock networks, in which the rise and/or fall time and amplitude of the clock waveform does not depend on the operating frequency, clock rise and/or fall time and amplitude in resonant distribution networks are a function of operating frequency, presenting another challenge in the design of resonant clock distribution networks. In particular, for fixed driver size and reference-clock duty cycle, the amount of energy supplied to the clock network at low clock frequencies is greater than at relatively higher clock frequencies, yielding shorter clock rise times and/or increased clock amplitudes. Therefore, to ensure that clock rise and/or fall times and amplitude meet their specification at every frequency, the size of the clock drivers or the duty cycle of the reference clock in a resonant clock network needs to be adjusted depending on clock frequency.
The use of resonant clock distribution networks is further complicated by the fact that in some circumstances it is desirable to completely disable the inductive elements, essentially using the clock drivers to swing the normally resonant clock distribution network in a “conventional mode”. With the inductive elements disabled, however, and therefore unable to provide any driving current to the clock distribution network, at any given clock frequency and with fixed driver size and reference-clock duty cycle, the amount of energy supplied to the clock network in resonant mode differs significantly from amount of energy supplied in conventional mode. As a consequence, to ensure that clock rise and/or fall times and amplitude meet their specification, the size of the clock drivers or the duty cycle of the reference clock in a resonant clock network needs to be adjusted, depending on operating mode.
In addition, since manufacturing variations will affect the actual capacitance of the resonant clock distribution network, the strength of the transistors used to implement the clock drivers, and duty cycle of the actual reference clock signal as it is delivered to the clock drivers, yet further adjustments to the size of the clock drivers or the target duty cycle of the reference clock will be needed, so that the clock signal meets its specification when in actual operation.
At-speed testing presents yet another challenge related with the use of resonant clock distribution networks in digital devices. In this kind of testing, a specific bit pattern is first loaded onto specified scan registers (scan-in mode) using a clock frequency that is significantly slower (for example, 5 times or more) than the target clock frequency that operation is to be tested at. The digital system is then operated for one or more clock cycles at the target clock frequency (at-speed-test mode), and to validate correct function, the contents of the scan registers are then read (scan-out mode) using a clock frequency that is once again significantly slower than the target clock frequency. Resonant clock distribution networks generally require multiple clock cycles of operation before they are able to provide their specified clock amplitude. Therefore, switching from scan-in mode to at-speed-test mode (or from at-speed-test mode to scan-out mode) is a challenge, due to the requirement for full-amplitude clock signals right from the beginning of the at-speed-test mode, and due to the difference in the clock frequencies between the scan modes and the at-speed-test mode. Furthermore, the great difference in clock frequency between scan modes and at-speed-test mode implies a significant difference in the rise and/or fall time of the clock waveform, and generally it is critical that the rise and/or fall times during at-speed testing match that of the resonant clock waveform at the same frequency when the network is operating in resonant mode.
It is possible to address the above challenges in ways that are likely to be impractical for many designs. For example, it is possible to select driver sizes and reference clock duty cycles that meet clock rise time and clock amplitude specifications for the fastest clock frequency at which the device is to be operated, and then use these same driver sizes and duty cycles at all other clock frequencies that may be required. In this case, however, at relatively low clock frequencies, energy consumption will be excessive, and clock amplitude will exceed the nominal voltage specified by the process, resulting in long-term reliability issues. In the context of at-speed test, it is possible to use a high-speed global enable signal to disable the clocked registers on the same clock cycle right after the last bit is scanned in, keep them disabled for as long as it takes for the resonant clock network to yield full-rail clock signals, and enable all clocked registers on the same cycle after the resonant clock signals has reached full rail. However, the design of a network that distributes such a high-speed enable signal with acceptable skew and correct relative timing with respect to the clock requires significant additional engineering effort and physical resources (for example, signal drivers and routing tracks).
Architectures for resonant clock distribution networks without programmable driver sizes or reference clock duty cycles have been described and empirically evaluated in the following articles: “A 225 MHz Resonant Clocked ASIC Chip,” by Ziesler C., et al., International Symposium on Low-Power Electronic Design, August 2003; “Energy Recovery Clocking Scheme and Flip-Flops for Ultra Low-Energy Applications,” by Cooke, M., et al., International Symposium on Low-Power Electronic Design, August 2003; and “Resonant Clocking Using Distributed Parasitic Capacitance,” by Drake, A., et al., Journal of Solid-State Circuits, Vol. 39, No. 9, September 2004. All of these papers are restricted to purely resonant clock distribution networks and make no reference to programmable driver sizes or reference clock duty cycles.
Designs for resonant clock distribution networks with programmable driver sizes and reference clock duty cycles have been described and empirically evaluated in the following articles: “A 1.1 GHz Charge Recovery Logic,” by Sathe V., et al., International Solid-State Circuits Conference, February 2006; “900 MHz to 1.2 GHz two-phase resonant clock network with programmable driver and loading,” by Chueh J.-Y., et al., IEEE 2006 Custom Integrated Circuits Conference, September 2006; “A 0.8-1.2 GHz frequency tunable single-phase resonant-clocked FIR filter,” by Sathe V., et al., IEEE 2007 Custom Integrated Circuits Conference, September 2007. All of these papers are restricted to resonant clock networks where programmable driver size and reference clock duty cycle have been purposed solely to reduce energy consumption, with no intent to control the rise time or amplitude of the clock waveform.
A resonant clock driver that is also capable of operating in conventional mode has been described in the article “A Resonant Global Clock Distribution for the Cell Broadband Engine Processor,” by Chan S., et al., IEEE Journal of Solid State Circuits, Vol. 44, No. 1, January 2009. However, the size of the clock drivers and the duty cycle of the reference clock in this article is fixed and therefore, it cannot be programmed depending on clock frequency or operating mode. Moreover, the article makes no reference to programmable clock driver sizes or reference clock duty cycles.
Overall, the examples herein of some prior or related systems and their associated limitations are intended to be illustrative and not exclusive. Other limitations of existing or prior systems will become apparent to those of skill in the art upon reading the following Detailed Description.